1. Field of the Invention
The present invention generally relates to the management of a program memory, that is, of a memory in which are stored applications containing instructions or opcodes to be executed by a processor, as opposed to a so-called data memory in which the variable data processed by a program are stored. Such a program memory generally is a non-volatile memory, possibly reprogrammable, storing program lines.
2. Discussion of the Related Art
An example of application of the present invention relates to JAVA applications intended to be processed within smart cards, that is, devices having a relatively reduced memory space, requiring segmentation of the memory to enable dynamic storage of the different applications.
More generally, the present invention applies to the management of program memory spaces in which the stored applications are to be stored at discontinuous addresses according to the space remaining available in the program memory.
Conventionally, upon initial storage of a program in a program memory, the processor associated with this memory loads the application into available areas or segments. The processor then also stores an address correspondence table enabling it to subsequently find back the instruction lines to be executed.
FIG. 1 shows a conventional example of a memory management unit (MMU) 1 generally used as an interface between a central processing unit 2 (UC) processing data from programs stored in a program memory 3 (MEM). The function of the interface is to convert a virtual address VIRTADD provided by central processor 2 into a physical address PHYSADD designating the memory line in which the desired instruction is stored in memory 3. Such a conversion is indispensable for instruction lines INST of the program to be able to transit from the memory to the central processor to be executed.
Upon installation of the program, that is, initial storage thereof in memory 3, central processor 2 generates an address-conversion table 12 keeping the correspondence between virtual addresses (successive program lines) and physical addresses of storage in memory 3 according to the available space therein and especially to the available segments. Afterwards, each time central processor 2 needs loading an instruction for execution thereof, it communicates the virtual address to interface 1 in charge of converting it into a physical address. In practice, to avoid slowing down the program execution, interface 1 requires a cache memory space 13 (CACHE) in which are temporarily stored the instructions between memory 3 and central processor 2. This cache memory is especially used to limit the extractions and conversions by avoiding extracting an instruction from memory 3 from the moment that it is available in the cache memory. A translation look-aside buffer 11 (TLB) then indicates to table 12 whether a segment is or not present in memory 13.
The memory management unit solution discussed in relation with FIG. 1 thus requires use of a cache memory. It is thereby incompatible with an application to integrated devices of limited size, especially of smart card type.
Further, the necessary address-to-address conversion devices and correspondence tables are particularly bulky.
The article “A Method L'article “A Method for Implementing Paged, Segmented Virtual Memories on Microprogrammable Computers” from Anderw S Tanenbaum, edited in 1979 in Operating Systems Review USA, vol. 13, no. 2, pages 26-32 (XP-002305693) discloses a method for converting an address of a program counter into an address in an external segmented memory. The change from a segment to another requires modifying the value of the program counter. Further, the detection of the segment boundaries depends on the information contained in the searched addresses.